In forming a dummy gate electrode in a RMG process, a thick oxide layer is formed on a substrate followed by a polysilicon or amorphous silicon layer, and a nitride capping layer, and the three layers are patterned and etched, for example by reactive ion etching (RIE). As illustrated in FIG. 1A, after etching the nitride capping layer 101, dummy gate 103, and oxide layer 105, a portion 107 of the oxide layer remains on the substrate 109 beyond the edge of the dummy gate. The oxide portion 107, or oxide footing, is difficult to remove without recessing the active surface of the substrate during the dummy gate RIE. As illustrated in FIG. 1B, spacers 111 are formed over the oxide footing 107.
In both planar and fin-type field effect transistor technologies, eSiGe is commonly employed for PFET source/drain regions for performance improvement. The eSiGe at the source/drain regions generates compressive stress to the channel which enhances hole mobility. For an eSiGe structure, both closer tip-to-tip (source-to-drain) and tip closer to the channel surface will introduce increased stress to the channel which further boosts mobility and performance. Such an eSiGe structure is referred to as “aggressive eSiGe”. Before eSiGe can be grown, a recess 113 is formed with SiCoNi material for a clean surface and growth interface. However, such materials etch away the oxide layer under the dummy gate at the source/drain boundaries (i.e., the oxide footing) at 115 in FIG. 1C, which is particularly problematic for aggressive eSiGe and will generate “mouse bite” defects. The mouse bite defects in turn introduce an effective channel 117 from the dummy gate to the bottom silicon substrate, as illustrated in FIG. 1D. During removal of the dummy gate to form a RMG, this channel 117 will serve as a weak point and result in an active region 119 hole defect, which reduces yield.
A need therefore exists for methodology enabling elimination of the mouse bite defects and the resulting devices.